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128 K x 32 Static RAM
PUMA68S4000X - 010/012/015/017
Issue 5.1 April 2001
Description
The PUMA68 range of devices provide a high density surface mount industry standard memory solution which may accommodate various memory technologies including SRAM, EEPROM and Flash. The devices are designed to offer a defined upgrade path and may be user configured as 8, 16 or 32 bits wide. The PUMA68S4000X is a 128Kx32 SRAM module housed in a 68 Jleaded package which complies with the JEDEC 68 PLCC standard. Access times of 10, 12, 15 and 17ns are available. The 5V device is available to commercial and industrial temperature grade.
Block Diagram
A0~A16 /OE /WE 128K x 8 SRAM /CS1 /CS2 /CS3 /CS4 D0~7 D8~15 D16~23 D24~31 128K x 8 SRAM 128K x 8 SRAM 128K x 8 SRAM
Features
* Access times of 10, 12, 15 and 17ns. * 5V + 10%. * Commercial and Industrial temperature grades * JEDEC Standard 68 PLCC footprint. * Industry standard pinout. * User configurable as 8 / 16 / 32 bits wide. * Operating Power (10ns-32 Bit) 3.96W (max) * Low power standby. (TTL) 1.16W (max) * Completely Static Operation.
Pin Definition See page 2.
Pin Functions
Description Address Input Data Input/Output Chip Select Write Enable Output Enable No Connect Power Ground Signal A0~A16 D0~D31 /CS1~4 /WE /OE NC VCC VSS
Package Details
Plastic `J' Leaded JEDEC PLCC Max. Dimensions (mm) - 25.27 x 25.27 x 5.08
Pin Definition - PUMA68S4000X
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Signal VCC NC /CS1 /CS2 /CS3 /CS4 NC NC D16 D17 D18 D19 VSS D20 D21 D22 D23 VCC D24 D25 D26 D27 VSS D28 D29 D30 D31 A6 A5 A4 A3 A2 A1 A0
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Signal VCC A13 A12 A11 A10 A9 A8 A7 D0 D1 D2 D3 VSS D4 D5 D6 D7 VCC D8 D9 D10 D11 VSS D12 D13 D14 D15 A14 A15 A16 /WE /OE NC NC
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Issue 5.1 April 2001
Absolute Maximum Ratings(1)
DC Operating Conditions
Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature DC Output Current
Symbol VT PT TSTG IOUT
Min -0.3 to
Max +7.0 4.0
Unit V W
O
-55
to
+125 20
C
mA
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Recommended Operating Conditions
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature (Commercial)
(Industrial)
Notes : (1) Pulse Width : -3.0V for less than 5ns.
Symbol VCC VIH VIL TA TAI
(1)
Min 4.5 2.2 -0.3 0 -40
Typ 5.0 -
Max 5.5 VCC+0.3 0.8 70 85
Unit V V V
O O
C C
(I Suffix)
DC Electrical Characteristics (VCC=5V+10%, TA=-40OC to 85OC)
Parameter Input Leakage Current Output Leakage Current Operating Supply Current
32 Bit 16 Bit 8 Bit
Symbol Test Condition ILI ILO ICC32 ICC16 ICC8 ISB
VIN=0V to VCC VI/O=0V to VCC CS =VIL,II/O=0mA, f=fMAX CS =VIL,II/O=0mA, f=fMAX CS =VIL,II/O=0mA, f=fMAX /CS =VIH,f=fMAX,VIN=VIL or VIH
(1) (1) (1) (1)
Min -20 -20 -
Typ -
Max 20 20 750 490 370 250
Unit A A mA mA mA mA
Standby Supply Current
TTL
Output Voltage Low Output Voltage High
Notes
VOL VOH
IOL=8.0mA, VCC = Min IOH=-4.0mA, VCC = Min
2.4
-
0.4 -
V V
(1) /CS1~4 inputs operate simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode. (2) At f=fMAX address and data inputs are cycling at max frequency (3) All currents are specified for 10ns
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Issue 5.1 April 2001
Capacitance (VCC = 5.0V, TA = 25OC, F=1MHz.)
Parameter Input Capacitance, (Address, /OE, /WE) Output Capacitance, 8 bit mode (worst case)
Note : These Parameters are calculated not measured.
Symbol CIN1 CI/O
Test Condition VIN=0V VI/O=0V
Min -
Typ Max 30 38
Unit pF pF
Test Conditions
* * * * * * Input pulse levels : 0V to 3.0V Input rise and fall times : 3ns Input and Output timing reference levels : 1.5V Output Load : See Load Diagram. VCC = 5V+10% PUMA module tested in 32 bit mode.
Output Load
I/O Pin
166 1.76V 30pF
Operation Truth Table
/CS1 /CS2 /CS3 /CS4 L H H H L H L L H H H L H L X H H L H H L H L H L H H L H L X H H H L H H L L H H L H H L L X H H H H L H L L H H H L H L L X H /OE X X X X X X X L L L L L L L H X /WE Supply Current L L L L L L L H H H H H H H H X ICC8 ICC8 ICC8 ICC8 ICC16 ICC16 ICC32 ICC8 ICC8 ICC8 ICC8 ICC16 ICC16 ICC32 ICC32/ICC16/ICC8 ISB,ISB1 Mode Write D0~D7 Write D8~D15 Write D16~D23 Write D24~D31 Write D0~D15 Write D16~D31 Write D0~D31 Read D0~D7 Read D8~D15 Read D16~D23 Read D24~D31 Read D0~D15 Read D16~D31 Read D0~D31 D0~D31 High-Z D0~D31 Standby
Notes : H=VIH : L=VIL : X=VIH or VIL
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Issue 5.1 April 2001
Read Cycle
10 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold From Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z 12 15 17
AC Operating Conditions
Symbol Min Max Min Max Min Max Min Max Units tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 10 2 3 0 0 0 10 10 5 5 4 12 3 3 0 0 0 12 12 6 6 5 15 3 3 0 0 0 15 15 7 8 7 17 3 3 0 0 0 17 17 8 9 8 ns ns ns ns ns ns ns ns ns
Write Cycle
10 Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Output Active from End of Write Data Hold time from Write Time Write to Output in High Z Symbol tWC tCW tAW tAS tWP tWR tDW tOW tDH tWHZ Min 10 9 9 0 8 0 6 0 0 Max 5 Min 12 10 10 0 9 0 7 0 0 12 Max 6 15 Min 15 12 12 0 10 0 9 0 0 Max Min 7 17 15 15 0 12 0 12 0 0 17 Max Units 8 ns ns ns ns ns ns ns ns ns ns
Under Development
PAGE 5
Issue 5.1 April 2001
Read Cycle 1 3,6,7,9 (Address Controlled)
Timing Waveforms
tRC Address tAA DOUT Data Valid tOH
Read Cycle 2 3,6,8,9 (/CS Controlled)
tRC1 /CS tOHZ tOE /OE tOLZ Data Valid DOUT Current Supply tCLZ tPU 50% tPD 50% ICC ISB tCHZ
Notes 1 During VCC power-up, a pull-up resistor to VCC on /CS is required to meet I SB specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 /WE is HIGH for read cycle. 7 /CS and /OE are LOW for Read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 /CS or /WE must be HIGH during address transitions. 11 All write cycle timings are referenced from the last valid address to the first transitioning address.
PAGE 6
Issue 5.1 April 2001
Write Cycle 1 10,11 (/WE Controlled)
tWC tAW Address
tAH
tWP /WE tAS tDW DIN tWZ DOUT Data Valid tOW tDH
Notes 1 During VCC power-up, a pull-up resistor to VCC on /CS is required to meet I SB specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 /WE is HIGH for read cycle. 7 /CS and /OE are LOW for Read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 /CS or /WE must be HIGH during address transitions. 11 All write cycle timings are referenced from the last valid address to the first transitioning address.
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Issue 5.1 April 2001
Write Cycle 2 10,11 (/CS Controlled)
tWC tAW Address tAS tCW /CS tAH
tWP /WE tWZ DIN tDW Data Valid tDH
DOUT
Notes 1 During VCC power-up, a pull-up resistor to VCC on /CS is required to meet I SB specification. 2 This parameter is sampled and not 100% tested. 3 For test conditions, see AC Test Conditions, Figures A, B, C. 4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500mV from steady-state voltage. 5 This parameter is guaranteed but not tested. 6 /WE is HIGH for read cycle. 7 /CS and /OE are LOW for Read cycle. 8 Address valid prior to or coincident with CS transition LOW. 9 All read cycle timings are referenced from the last valid address to the first transitioning address. 10 /CS or /WE must be HIGH during address transitions. 11 All write cycle timings are referenced from the last valid address to the first transitioning address.
PAGE 8
Issue 5.1 April 2001
Package Details
PUMA 68 pin JEDEC Surface Mounted PLCC
Pin 1
Pin 68
25.27 (0.995) 25.02 (0.985) 5.08 (0.200) max
0.46 (0.018)
1.27 (0.050)
0.90 (0.035) typ
23.11 (0.910) 24.13 (0.950)
PAGE 9
Issue 5.0 August 1999
Ordering Information
Ordering Information
PUMA 68S4000XLI - 010
Speed 010 012 015 017 = = = = 10ns 12ns 15ns 17ns
Temp. Range/Screening Blank = Commercial I = Industrial Power Consumption Pinout Configuration Memory Organisation Blank = Standard X = Industry Standard Pinout 4000 = configurable as 128K x 8, 256K x 16 or 512K x 8 S = SRAM PUMA 68 = 68 pin `J' Leaded PLCC
Technology Package
Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director.
PAGE 10
http://www.mosaicsemi.com/
Issue 5.1 April 2001
Customer Guidelines
Visual Inspection Standard
All devices inspected to ANSI/J-STD-001B Class 2 standard
Moisture Sensitivity
Devices are moisture sensitive. Shelf Life in Sealed Bag 12 months at <40OC and <90% relative humidity (RH). After this bag has been opened, devices that will be subjected to infrared reflow, vapour phase reflow, or equivalent processing (peak package body temp 220OC) must be : A : Mounted within 72 Hours at factory conditions of <30OC/60% RH OR B : Stored at <20% RH If these conditions are not met or indicator card is >20% when read at 23OC +/-5% devices require baking as specified below. If baking is required, devices may be baked for :A : 24 hours at 125OC +/-5% for high temperature device containers OR B : 192 hours at 40OC +5OC/-0OC and <5% RH for low temperature device containers.
Packaging Standard
Devices packaged in dry nitrogen, JED-STD-020. Packaged in trays as standard. Tape and reel available for shipment quantities exceeding 200pcs upon request.
Soldering Recomendations
IR/Convection Ramp Rate Temp. exceeding 183OC Peak Temperature Time within 5OC of peak Ramp down Ramp up rate Peak Temperature Time within 5OC of peak Ramp down 6OC/sec max. 150 secs. max. 225OC 20 secs max. 6OC/sec max. 6OC/sec max. 215 - 219OC 60 secs max. 6OC/sec max.
Vapour Phase -
The above conditions must not be exceeded.
Note : The above recomendations are based on standard industry practice. Failiure to comply with the above recomendations invalidates product warranty.
PAGE 11
Issue 5.1 April 2001

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